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p/n: pm0365 1 features ? control C controller and integrated bus interface total solu- tion for ieee 802.3, 10base5, 10base2 and 10base-t C software-compatible with industry standard ethernet adapters: * novell?'s ne 2000 * western digital/smc's (8003e, 8003ebt, 8013ebt) C selectable buffer memory size C no external bus logic or drivers C integrated controller, mcc and transceiver C full ieee 802.3 aui interface C single 5v supply C software-compatible with dp8390, dp83901 and dp83902 C efficient buffer management implementation ? mcc module (manchester code converter, also called endec) C 10 mbit/s manchester encoding/decoding C squelch on receive and collision pairs ? tpi module (10base-t) transceiver C transmitter and receiver functions C collision detect, heartbeat and jabber C selectable link integrity test or link disable C polarity detection/correction ? provides more powerful functions than ns dp83905 C supports 15 i/o bases instead of 7 C direct id prom access through i/o port instead of through remote dma C auto configuration function-supported makes jumperless more powerful C solution for multiple lan cards i/o bases conflict problem to make manufacture more efficient. C supports "write id back to eeprom" function instead of just writing configuration back to eeprom to make manufacture more efficient. C modify current configurations without turning off power C variety of eeprom supported general description the mx98905 is designed for easy implementation of csma/cd local area networks, which include ethernet? (10base5), thin ethernet (10base2), and twisted-pair ethernet (10base-t). the media ac- cess control (mac) and encode-decode (endec) are provided with an aui interface. the 10base-t transceiver functions according to the ieee 802.3 standards, and the mx98905 10base-t transceiver operations in compliance with the ieee standard. the functional block of the mx98905 consists of the integration of the entire bus interface for pc-at? (industry standard architecture, isa) bus-based sys- tems, receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity blocks. when combined with equalization resistors, the transceiver transmits or receives filters, and pulse transformers provide physical interface from the endec module of the mx98905 and the twisted-pair medium. when software and hardware are properly configured, the mx98905 can be set to be compatible with either the ne2000 or ethercard plus16?. all bus drivers and control logic are integrated inside the chip to reduce lan card cost and area. manchester encoding and decoding is made possible through the integrated endec by means of a differ- ential transceiver and phase lock loop decoder at 10 mbit/sec. collision detect translator and diagnostic loopback capability are included in this process. interfacing directly with the transceiver module, the endec module also provides a fully ieee-compliant aui (attachment unit interface) to connect with other media transceivers. the media access control function, provided by the ethernet network control (enc) module, effects an efficient packet transmission and reception control through unique dual dma channels and an internal fifo. to lessen board cost and area overheads, bus arbitration and memory control logic are integrated. designed for easy interface with other transceivers by means of the aui interface, the mx98905 provides a thorough single chip solution for 10base-t ieee 802.3 network. constraints of cmos processing require that isolation, whether capacitive or inductive, be used at the aui differential signal interface for 10base5 and 10base2 applications. rev. 1.3, nov 20 ,1995 mx98905b
2 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b note: tri-state? is a registered trademark of national semiconductor. pc-at? is a register trademark of international business machines corp. novell? is a registered trademark of novell inc. ethercard plus? and ethercard plus 16? are trademarks of standard microsystems corp. ethernet? is a registered trademark of xerox corp.
3 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b pin configuration 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 vcc aen chrdy gnd gnd reset sd0 sd1 gnd sd2 sd3 vcc sd4 sd5 gnd sd6 sd7 gnd vcc gnd txm txp vcc vcc rxm rxp cdm cdp gnd rxip rxim vcc txodm txop txom txodp vcc gnd gnd vcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 la21 la20 la19 la18 la17 mrdl mwrl sd8 sd9 gnd sd10 sd11 vcc sd12 sd13 gnd sd14 sd15 lowpwr atxt gnd vcc memd0 memd1 memd2 memd3 gnd memd4 memd5 memd6 memd7 vcc memd8 memd9 memd10 memd11 gnd memd12 memd13 memd14 gdlinkl poledl coledl rxledl txledl gnd x1 x2 vcc thin test bsclk vcc gnd mema15 mema14 mema13 mema12 mema11 mema10 mema9 mema8 gnd vcc mema7 mema6 mema5 mema4 mema3 mema2 mema1 mswrl msrdl rcs2l gnd rcs1l bpcsl eecs eeconfig memd15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 smwrl smrdl iowrl iordl gnd sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 vcc sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 gnd sa3 sa2 sa1 sa0 isaclk int3 int2 int1 int0 bale vcc m16l gnd io16l sbhel la23 la22 mx98905b
4 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b pin descriptions a. isa bus interface symbol pin type pin number description sa0-sa19 i 94-97, 99-106, latched address bus: low-order bits of the system's 24-bit address bus. these lines are enabled onto the bus when bale is high and latched when bale is deasserted. the mx98905 uses these bits to decode the boot prom address and internal registers. in shared memory mode, they are used to decode accesses to memory of the mx98905. la17-la23 i 76-82 unlatched address bus: high-order 7 bits of the 24-bit system address bus. these lines are valid on the falling edge of bale. the mx98905 uses these bits to decode shared memory address in shared memory mode. the validity of m16l depends on these signals only. sd0-sd15 i/o 127, 128, 130, system data bus: 16-bit system data bus. used to transfer data between the system and the mx98905. 136, 137, 73, 72 70, 69, 67, 66, 64, 63 bale i 88 bus address latch enable: active-high signal. used to latch valid addresses from the current bus master on the falling edge of bale. sbhel i 83 system bus high enable: active-low. indicates that the system expects a transfer on the address on the bus is 16 bits wide. io16l o 84 16-bit i/o transfer: active-low. in i/o mode this signal indicates that the mx98905 is responding to a 16-bit i/o access by driving 16 bits of data on sd0-sd15. m16l o 86 16-bit memory transfer: active-low. mwrl i 74 memory write strobe: active-low. system uses this signal to write to the memory map of the mx98905. mrdl i 75 memory read strobe: active-low. system uses this signal to read from the memory map of the mx98905. smrdl, i 119, 120 low memory strobes: active-low. the mx98905 uses mrdl and mwrl in 16-bit memory mode and will use smrdl and smrl in memory mode when atxt is low (8-bit mode). note that smrdl and smwrl are also used to access the boot prom. iowrl i 118 i/o write strobe: active-low. strobe from system to write to the i/o map of the mx98905. iordl i 117 i/o read strobe: active-low. strobe from system to read from the i/o map of the mx98905. 108-115 smwrl 131, 133, 134,
5 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b a. isa bus interface (continued) symbol pin type pin number description reset i 126 reset : active high. used to reset all devices on the bus. the mx98905 will recognize this signal only when the duration of this signal is larger than 400 ns. chrdy o 123 channel ready: used to insert wait states into system accesses. aen i 122 dma active: indicates that the address lines are driven by a dma controller. int0-int3 o 89-92 interrupt request: activation or not of these 4 signals is determined by configuration registers a and c. they can be used to either directly drive the interrupt lines or used as a 3-bit code with strobe to generate up to 8 interrupts. atxt i 61 8/16 bit slot select: indicates that the mx98905 is in 8- or 16- bit isa bus. it is in 16-bit mode when atxt is high atxt has internal pulldown register; if left unconnected, 8-bit mode is the default mode. isaclk i 93 isa clock: clock from isa bus.
6 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b b. network interface symbol pin type pin number description poledl o 2 polarity led: active-low signal. when the mx98905 detects seven consecutive link pulses or three consecutive received packets with reversed polarity, poledl is asserted. txledl o 5 transmit led: active-low signal. it is asserted for approximately 50ms whenever the mx98905 transmits data in either aui or tpi modes. rxledl o 4 receive led: active-low signal. an open-drain output. it is asserted for approximately 50ms whenever valid received data is detected while in aui or tpi modes. coledl o 3 collision led: an open-drain active-low signal. it is asserted for approximately 50ms whenever collision is detected while in aui or tpi modes. gdlinkl o 1 good link led: an open-drain active-low signal. used to display link integrity status. off (when high): a. mx98905 is in aui mode b. mx9805e is in tpi mode, link testing is enabled and link integrity is bad. on (when low): a. link testing is disabled b. link testing is enabled and link integrity is good. x1 i 7 crystal or external oscillator input. x2 o 8 crystel feedback output: used in crystal connection only. should be left completely unconnected when using an oscillator module. thin o 10 thin cable: active-high signal. it is high when the mx98905 is configured for thin cable (program phy1 and phy0 of configuration b). this signal can be used to turn on the dc-dc converter required by thin ethernet. txodp, o 156-153 twisted-pair transmit outputs: these high-drive cmos level outputs are resistively combined external to the chip to produce a differential output signal with equalization to compensate for inter- symbol interference (isi) on the twisted-pair medium. txom, txop, txodm
7 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b b. network interface (continued) symbol pin type pin number description rxip, rxim i 150-151 twisted-pair receive inputs: these inputs feed a differential amplifier which passes valid data to the mcc module. txm, txp o 141-142 aui transmit output: differential driver which sends the encoded data to the transceiver. the outputs are source follower which requires 270 w pulldown resistors. rxm, rxp i 145-146 aui receive inputs: differential receive input pair from the transceiver. cdm, cdp i 147-148 aui collision inputs: differential collision pair input from the transceiver cable.
8 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b c. external memory support symbol pin type pin number description memd0-7 i/o 58-55 memory support data bus; configuration register a input; eeprom signals. memd0-7 : these pins can be used to access external memory (ram) and boot prom while reset is inactive. ca0-7: when reset is active more than 400 m s, configuration register a is loaded with the value on these pins on the falling edge of reset signal. these 8 bits have internal pulldown resistors, hence if the pin is left unconnected the corresponding register bit is 0. do, di, sk: when reset goes from an active to an inactive level, the mx98905 will read the contents of an eeprom. at this moment, do = memd0, di = memd1 and sk = memd2. the value read from eeprom will be stored in configuration registers and prom space. memd8-15 i/o 48-45 memory support data bus; configuration register b input. memd8-15 : these pins can be used to access external memory when reset is inactive. cb0-7 : when reset is active more than 400 m s, configuration register b is loaded with the value on these pins on the falling edge of reset signal. these 8 bits have internal pulldown registers, hence if the pin is left unconnected the corresponding register bit is 0. mema1-8 i/o 31-25, 22 memory support address bus; configuration regis- ter c input. mema1-8 : these pins can be used to drive external memory address bus when reset is inactive. cc0-7 : when reset is active more than 400 m s, configuration register c is loaded with the value on these pins on the falling edge of reset signal. for application without eeprom (i.e. eeconfig is low) and try to load configuration data to cc from these eight pins, external resistor is necessary. mema9-15 o 21-15 memory support address: these pins can be used to drive external memory address bus when reset is inactive. when the memory is only 8 bits wide (single ram) and the mx98905 is in compatible mode, a0 will appear on a13; and on a15 in non- compatible mode. msrdl o 33 memory support bus read: strobes data from the external ram into the mx98905 through the memory support data bus. mswrl o 32 memory support bus write: strobes data from the mx98905 into the external ram via the memory support data bus. bpcsl o 37 boot prom chip select: active-low signal for selecting the boot prom. ca0-7 do, di, sk
9 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b c. external memory support (continued) symbol pin type pin number description rcs1l o 36 ram chip select 1 : active-low signal to drive the cs signal of the external ram on the lower half of the memory-supported data bus. rcs2l o 34 ram chip select 2: active-low signal to drive the cs signal of external ram on the upper half of the memory-supported data bus. eecs o 38 eeprom chip select: active-high signal to drive the cs signal of the external eeprom. eeconfig i 39 configure from eeprom: the mx98905 will not load configu- rations from eeprom if this pin is low during power-on reset. bsclk i 12 internal bus clock: this pin controls the speed of the controller dma function. when clksel of configuration c is set low, this pin should be tied to ground. d. low power support symbol pin type pin number description lowpwr i 62 low power: when it is high, the mx98905 enters its low-power mode. this pin should be tied to ground for normal operation. e. test support symbol pin type pin number description test i 11 test: this pin is only used for industry test. it should be left unconnected in normal operation (because it has internal pulldown resistor).
10 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b f. power supply pins symbol pin type pin number description vcc i 160, 157, 152, 5v power supply pin. 144, 143, 9, 59, 49, 24, 13, 132, 121, 107, 87, 68,139 gnd i 159, 158, 149, gnd supply pin. 140, 138, 6, 60, 54, 44, 35, 23, 14, 135, 129, 125, 124, 116, 98, 85, 71, 65
11 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b functional description 1. i/o bases determination the i/o bases are determined by 6 bits in the mx98905. they are: ioad2-0 in configuration a (ca); page and ioben in hidden configuration register (hcfr) and hcfre in hidden command register (hcmr). for details about hcmr and hcfr (registers provided by the mx98905 only) see register description. user can directly modify the value of page and ioad2-0 to change i/o base or use auto configuration feature provided by the mx98905. see enhanced mode description for details about auto configuration. the following are the i/o bases mapping: table 1. i/o bases mapping hcmr hcfr hcfr ca hcfre ioben page ioad2 ioad1 ioad0 i/o base 0 x x 0 0 0 300h 1 x x 0 0 1 not supported 0 x x 0 1 0 240h 0 x x 0 1 1 280h 0 x x 1 0 0 2c0h 0 x x 1 0 1 320h 0 x x 1 1 0 340h 0 x x 1 1 1 360h 1 0 x 0 0 0 300h 1 0 x 0 0 1 not supported 1 0 x 0 1 0 240h 1 0 x 0 1 1 280h 1 0 x 1 0 0 2c0h 1 0 x 1 0 1 320h 1 0 x 1 1 0 340h 1 0 x 1 1 1 360h 1 1 0 0 0 0 300h 1 1 0 0 0 1 not supported 1 1 0 0 1 0 240h 1 1 0 0 1 1 280h 1 1 0 1 0 0 2c0h 1 1 0 1 0 1 320h 1 1 0 1 1 0 340h 1 1 0 1 1 1 360h
12 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b hcmr hcfr ca hcfre ioben page ioad2 ioad1 ioad0 i/o base 1 1 1 0 0 0 380h 1 1 1 0 0 1 3a0h 1 1 1 0 1 0 3c0h 1 1 1 0 1 1 3e0h 1 1 1 1 0 0 200h 1 1 1 1 0 1 220h 1 1 1 1 1 0 2a0h 1 1 1 1 1 1 2e0h hcfre, ioben and page are powered on low if soft- ware driver doesn't alter the value of these bits. the i/o bases of the mx98905 are fully compatible with dp83905.
13 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 2. shared memory compatible mode this mode is compatible with the ethercard plus16. i/ o address mapping and memory mapping will be de- scribed subsequently. after i/o base is determined, the following structure appears: 2.1 i/o address mapping figure 2. shared memory mode register mapping base + 00h base + 01h base + 05h base + 08h base + 0fh base + 10h base + 1fh at detect prom mx9890 core registers control1 control2 iordl iowrl the at detect register indicates whether the mx98905 is in an 8- or 16-bit slot. the mx98905 uses the falling edge of reset to latch the value shown on atxt to determine the value of atdet. address 08h to 0fh are specified as prom space. the contents of prom are loaded from eeprom during power-on reset. user should program the eeprom to contain these value. in enhanced mode of the mx98905, the contents of prom can be written back to eeprom. see enhanced mode description for details. 2.2 memory address mapping figure3. shared memory mode enc core memory map 0000h 4000h 8000h c000h ffffh 8kx16 buffer ram aliased buffer ram aliased buffer ram aliased buffer ram d15 d0 figure 4. shared memory mode host memory map for 8 kbytes buffer ram base + 0000h base + 3fffh 8kx8 buffer ram d15 d0 figure 5. shared memory mode host memory map for 16 kbytes buffer ram base + 0000h base + 7fffh 16kx8 buffer ram d15 d0
14 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b the 8 kwords of memory can be accessed directly by the host system in the same manner as any other memory. typically the programmer can remove data from this buffer using a "mov" or "movsw" instruction. in compatible mode, data located at address 4000h- 7fffh, 8000h-bfffh and c000h-ffffh is just the mirror of contents located at 0000h-3fffh. 2.3 configuration vs. operation memw comp size atdet mx98905 access mode host access mode 0 0 8k 0 byte byte 0 0 8k 1 byte byte 1 0 16k 0 byte/word byte 1 0 16k 1 byte/word byte/word 0 1 32k 0 byte byte 0 1 32k 1 byte byte 1 1 64k 0 byte/word byte 1 1 64k 1 byte/word byte/word 2.4 sram size vs. mema[15:1] sramsize mema15 mema14 mema13 rcs1l rcs2l 8k 0 1 a0 even/odd x 16k 0 1 a13 even odd 32k a0 a14 a13 even/odd x 64k a15 a14 a13 even odd
15 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 3. shared memory non-compatible mode the difference between compatible and non- compatible mode is that the non-compatible mode maps a full 64 kbytes of ram into the pc's memory address space instead of 8 kbytes. the i/o map for both modes is the same. 4. 16-bit i/o port compatible mode this mode is compatible with the novel ne2000. i/o address mapping and memory mapping will be shown in the following subsection. after i/o base is determined, the following structure appears: 4.1 i/o address mapping figure 6. i/o mode i/o port map base + 00h base + 0fh base + 10h base + 17h base + 18h base + 1fh mx9890 core registers d15 d0 data transfer port reset port 4.2 memory address mapping figure 7. i/o mode memory map the registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. by programming the enc's internal registers, the user can issue remote dma to transfer data between the data port and the external memory. 0000h 001fh 4000h 7fffh 8000h c000h ffffh prom d15 d0 aliased prom 8kx16 buffer ram aliased prom aliased buffer ram the mx98905 controller has a 64k address range, but only does partial decoding on these devices. the prom data is mirrored at all decodes up to 4000h and the entire map is repeated at 8000h. in order to access either the prom or the ram, the user must initiate a remote dma transfer between the i/o port (see i/o map) and the memory. address 00h to 1fh are specified as the prom space to make the mx98905 compatible with ne2000. simi- lar to shared memory map, this is actually an array of 8-bit registers which are loaded from eeprom during power-on reset. user should prepare data in the eeprom as show in the format. for user's convenience, the mx98905 provides an enhanced mode to facilitate software to access the contents of id prom -- read id prom through i/o port. user can refer to enhanced mode description for details.
16 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 4.3 prom map table 2. prom location location contents 00h ethernet address 0 (msb) 01h ethernet address 1 02h ethernet address 2 03h ethernet address 3 04h ethernet address 4 05h ethernet address 5 06h-0dh 00h 0e-0fh 57h 10-15h ethernet address 0 thru 5 16-1dh reserved 1e-1fh 42h the upper two addresses of the prom store contain bytes that identify whether the mx98905 controller is in 8- or 16-bit mode. for 16-bit mode the values of these bytes are 57h; for 8-bit mode they both contain 42h. software driver can read these two bytes to determine whether the controller is in 8- or 16-bit mode. 5. 8-bit i/o port compatible mode in 8-bit i/o port compatible mode, the i/o mapping is the same as in 16-bit mode. the memory map for 8-bit i/o port compatible mode is shown below: figure 8. i/o mode 8-bit memory map 0000h 001fh 4000h 5fffh d15 d0 unused 8kx16 buffer ram prom 6. i/o port non-compatible mode although this mode is similar to novell's ne2000, it also allows the user to use the full 64 kbytes of address space except for an initial page for the prom. i/o map is the same as compatible mode. memory map is shown below: figure 9. i/o mode non-compatible mode memory map 0000h 00ffh 0100h ffffh d15 d0 buffer ram prom although the prom occupies 256 bytes, it is only 16 bytes long. there is a partial decode inside the mx98905 so the prom is mirrored at 16 addresses in this region. 7. power-on reset operation when the duration of reset signal is longer than 400ns, the mx98905 will read configurations from eeprom depending on the value shown on eeconfig pin. user should prepare all the data the mx98905 needs in the eeprom before switching on the pc. the following table shows the format of eeprom:
17 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b table 3. eeprom data mapping 0fh 0eh 08h 07h 03h 02h 01h 00h d15 d0 not used config. b 42h 57h reserved (checksum) etehr add 5 ether add 3 etehr add 1 config. c config. a 42h 57h reserved (board type) ether add 4 etehr add 2 etehr add 0 except the reset signal. on the falling edge of reset signal, the mx98905 will load data shown on memd0-7, memd8-15 and mema1-8 into configuration register a, b and c, respectively. the value loaded from jumper will overwrite the default value. figure 10 shows the example for jumper configuration. after loading jumper value into relative configuration registers, the mx98905 will execute eeprom opera- tion, which depends on the value of eeconfig. if eeconfig is high, then both the configuration and id prom data will be loaded into the mx98905; other- wise, only id prom data is loaded. 7.2 eeprom operation during eeprom operation, all internal registers are inaccessible. if eeconfig is high, then the configu- rations loaded from eeprom will overwrite the value loaded from jumper selection. configurations loaded from eeprom will be stored in configuration registers and ether id will be stored in prom space inside the mx98905 (refer to prom map for details). 7.2.1 load configurations from eeprom when eeconfig is set to high, configurations stored in epprom will be loaded into mx98905. after loading configurations fom eeprom, following sequence depends on the value of atxt: atxt= 1 : 00h-07h atxt= 0 : 00h-06h, 08h eeconfig = 1 : oeh (configuration a, b), ofh dwid = 1 (configuration c),00h - 02h (ether address 0 theu 5) and 03h - 07h eeconfig = 1 : oeh (configuration a, b), ofh dwid = 0 (configuration c),00h - 02h (ether address 0 true 5)and 03h - 06h and 08h (data 42h) values shown on parentheses are for shared memory map only. for the shared memory mode, the two's complement of these eight bytes (00-03h) should be equal to ffh. high byte of 0fh is not used in ns dp83905 compat- ible mode, but the value will be loaded into hidden configuration register (hcfr) inside the mx98905 in enhanced mode. see enhanced mode description for details. 7.1 valid power-on reset the mx98905 is equipped with a filter to screen out reset signal whenever its duration is less than 400ns. the default value of each configuration register is: configuration register a : 39h configuration register b : 00h configuration register c : 00h when reset is active more than 400ns, the mx98905 will recognize such action and begin its power-on reset algorithm. at this moment, all i/o will be disabled 7.2.2 without loading configurations from eeprom when eeconfig is set to low, configrations stored in eeprom will not be loaded into the mx98905 de- pends on the value of atxt: atxt = 1 : 00h-07h atxt = 0 : 00h-06h,08h
18 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 8. storing configuration back to eeprom to write configuration into the eeprom, user must follow the procedure specified below: eeprom_store ( ) { disable_all_interrupts ( ) ; value = read (cb) ; value = value & gdlink ; value = value eestore ; write (cb, value) ; / / issue eestore / / eestore algorithm starts read (cb) ; write (cb, value_for_ca) ; / / write new / /into ca through cb write (cb, value_for_cb) ; / / write cb write (cb, value_for_cc) ; / / write new value into cc through cb while (value & eestore) { value = read(cb) ; wait ( ) ; } enable_all_interrupts ( ) ;
19 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b figure 10. example of jumper configuration mema5 mema4 mema3 mema2 mema1 in in in in out out out out mema8 mema7 mema6 vdd resistor resistor resistor resistor memd11 memd10 memd9 in in in out out out memd15 memd14 memd13 memd12 resistor resistor resistor memd8 memd7 memd6 memd5 memd4 memd3 memd2 memd1 memd0 in in in out out out resistor resistor resistor in in in out out out resistor resistor resistor data loaded to cc 1eh data loaded to cb 0eh data loaded to ca fch resistor resistor resistor resistor resistor resistor resistor resistor note:pull down resistors(4.7ky~10ky) are required to be connected to mema8~mema1.
20 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b after eeprom_store is executed, the current con- figuration will not be changed. if user wants to use the new configuration, he should turn the power off and then turn it on to load new configuration into the mx98905 through valid power-on reset. for user's convenience, the mx98905 provides the feature for software programmer to update the current configuration after eeprom_store is executed, i.e., you don't have to switch the power to update the configuration. see enhanced description for details. 9. enhanced feature functional descrip- tion there are two registers, hcmr and hcfr which control the main fuctions of mx98905's enhaned mode. hcmr is the abbreviation of hidden command register and hcfr for hidden configuration register. bit assignment and function of each bit of hcmr and hcfr will be fully descibed in register descrip- tions. for your quick reference, bit assignments of hcmr and hcfr are shown below before we present the enhanced features of mx98905. the following shows the bit assignment for hcmr: following shows the bit assignment for hcfr 9.1 load hcfr from eeprom the high-byte value of address 0fh of eeprom will be loaded into hidden configuration register (hcfr) if a valid power-on reset is detected by the mx98905. hcfr is only active when hcfre bit of hcmr (hidden command register, supported by the mx98905) is set high. if software doesn't alter the value of hcfre, the value in hcfr has no effect. in the same way, when eeprom_store algorithm is executed, contents of hcfr will be stored back to eeprom at the location from where they come. npgen multi allwr resvd idecmd pgsel hcfre auto resvd ioben page newcf locke resvd resvd resvd 9.2 16 bytes idprom write back function to write configuration into the eeprom in either mx98905 or mx98905a, user must follow the procedure described in section 8. in mx98905, a "1" value in allwr bit will cause the controller to write ca, cb, cc and id to eeprom. while in mx98905a, a "1" value in allwr bit will write ca, cb, cc, id, and the rest of 8 bytes from idprom registers. i.e. the entire 16 bytes of idprom registers can be written back to eeprom. the other eeprom write back command is idwcmd command whose function remains the same as old version. when loading data from eeprom during power-on reset, values in idprom register byte 15th and 16th are never written back to eeprom but initialized to correct value according to slot's data width during power-on reset. these two bytes can be modified through software programming. 9.3 update current configuration after eeprom_store is finished when newcf bit of hcfr is set, the contents of ca, cb and cc will be updated to the value in eeprom_store algorithm after eeprom_store algorithm is finished. user doesn't have to switch the power to use the new configu- ration. 9.4 access id prom through i/o port in ne2000 compatible when npgen is high and pgsel is low (both in hcmr), the mx98905 is programmed to new page 0. contents of id prom can be directly accessed through i/o port. table 4 and table 5 show the address mapping. 9.5 auto configuration the mx98905 provides a powerful feature for pro- grammer to program the lan card in order to avoid the "io base is conflict with other add_ on cards" program. when bit 3 (auto) of hcmr is set to 1, the mx98905 will change the internal io base automatically. when software writes to auto the first time, the io base will change to 300h no matter the current io base is. susbsequent writing to auto bit will make the mx98905 jump to the "next" io base as described in next paragraph. after auto is issued, user can use the information provided below to read the autostatus
21 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b register (asr) to determine whether the io base is conflict with other add_ on card(s) or not. when 15 io base is not enabled (see hcmr register description for more detail), internal state machine will only support 7 io bases when auto is written; if ioben of hcfr is set to high (see hcfr register description for more detail), the internal state machine will alter the value of page of hcfr automatically when further io base is necessary during auto configuration. the following i/o bases are supported by mx98905. (*) represents that the io bases are not supported by mx98905 when 15 io base is not enabled. 200h (*), 220h (*), 240h, 280h,2a0h (*), 2c0h, 2e0h (*), 300h, 320h, 340h, 360h, 380h (*), 3a0h (*), 3c0h (*) , and 3e0h (*) the following io base and its relative asr value (shown in parenthses) will be followed after software write an "1" to auto bit of hcmr.
22 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b table 5. new page 0 address assignment for memory map sa00..3 read write 00h control 1 control 1 01h at detect reserved 02h reserved reserved 03h reserved reserved 04h reserved reserved 05h control 2 control 2 06h reserved reserved 07h reserved reserved 08h prom byte #0 (pb0) prom byte #0 (pb0) 09h prom byte #1 (pb1) prom byte #1 (pb1) 0ah prom byte #2 (pb2) prom byte #2 (pb2) 0bh prom byte #3 (pb3) prom byte #3 (pb3) 0ch prom byte #4 (pb4) prom byte #4 (pb4) 0dh prom byte #5 (pb5) prom byte #5 (pb5) 0eh prom byte #6 (pb6) prom byte #6 (pb6) 0fh prom byte #7 (pb7) prom byte #7 (pb7) table 4. new page 0 adderss assignment for i/o map sa00..3 read write 00h prom byte #0 (pb0) prom byte #0 (pb0) 01h prom byte #1 (pb1) prom byte #1 (pb1) 02h prom byte #2 (pb2) prom byte #2 (pb2) 03h prom byte #3 (pb3) prom byte #3 (pb3) 04h prom byte #4 (pb4) prom byte #4 (pb4) 05h prom byte #5 (pb5) prom byte #5 (pb5) 06h prom byte #6 (pb6) prom byte #6 (pb6) 07h prom byte #7 (pb7) prom byte #7 (pb7) 08h prom byte #8 (pb8) prom byte #8 (pb8) 09h prom byte #9 (pb9) prom byte #9 (pb9) 0ah prom byte #10 (pb10) prom byte #10 (pb10) 0bh prom byte #11 (pb11) prom byte #11 (pb11) 0ch prom byte #12 (pb12) prom byte #12 (pb12) 0dh prom byte #13 (pb13) prom byte #13 (pb13) 0eh prom byte #14 (pb14) prom byte #14 (pb14) 0fh prom byte #15 (pb15) prom byte #15 (pb15)
23 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 9.6 write network id back to eeprom the programmer has two approaches to store network id back to eeprom. they are: 1. store network id only 2. store configuration and network id at the same time for case 1, the following procedure should be followed exactly: id_store ( ) { program_to_new_page_0 ( ) ; / / see register description if (necessary) modify_prom_byte0_5 ( ) ; program_to_new_page_1 ( ) ; / / see register description write (hcmr, '16h') ; / / issue idwcmd value = read (hcmr) ; while (value & idwcmd) { value = read (hcmr) ; wait ( ) ; } write (hcmr, '00h') ; / / back to normal mode } the following pseudo c code algorithm is for case 2: all_store ( ) { program_to_new_page 0 ( ) ; / / see regsiter description if (necesary) modify_prom_byte0_7 ( ) ; program_to_new_page_1 ( ) ; / / see register description write (hcmr, '20h') ; / / enable all write algorithm eeprom_store ( ) ; / / call eeprom_store subroutine} note:only prom byte 0-7 will be written back to eeprom when all_store() is issued.
24 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b by the way, when the guessed value is hit the network i.d., a register call signature (with value 78h, 'x') will be realeased by mx98905. if software can properly read the contents of signature and asr, then a conflit free io base is found. if software can't access the value of signature but asr, then the guessed value is wrong. if software can't access the value of signature nor asr, then mx98905(s) is conflict with other add_on cards. in case signature can be accessed by software, then user can write 1 to locke bit of hcfr through port "nonconflict_iobase+08h". the io base of this lan card will be locked all the time to prevent it from jumpping to other io base when auto is issued. see application notes or call se/fae if you have any ques- tions. 9.6.1 7 io bases supported 300h (18h ) -> 240h (22h) -> 280h (34h) -> 2c0h (46h) -> 320h (59h) -> 340h (64h) -> 360h (0bh) - > 300h -> (18h) (cyclic) 9.6.2 15 io bases supported 300h (18h) -> 240h (22h) -> 280h (34h) -> 2c0h (46h) -> 320h (59h) -> 340h (6ah) -> 360h (7bh) - > 380h (8ch) ->3a0h (9dh) -> 3c0h (aeh) -> 3e0h (bfh) -> 200h (c0h) -> 220h (d1h) -> 2a0h e5h) - > 2eh (07h) -> 300h (18h) (cyclic) 9.7 multiple lan card auto configuration to faciliate one to understand the "mutiple lan card auto configuration ", an example is shown below: (follow the steps shown in application note) condition : one lan card with network id 001111001001 : the second lan card with network id 0022220308 1. at the beginning, software first write auto. the io base of both lan card will be changed from their current io bases to 300h. 2. software guesses 00h, then write auto. because the guessed i.d. (sid) hits the network i.d. on both lan card, the io bases of these two lan cards will jump to 240h (assume software choose 7 io bases) 3. software guesses 01h, then issue auto. the software guessed i.d. (sid) hits the network i.d. (hid) of the first card, hence the io base of the first card will stay at 240h and the io base of the second card jumpped to 280h. software can access "x" (78h,signature register) from io base 248h. 4. software write 1 to locke bit to lock the first card. 5. software keep guessing and writing 1 to auto. finally, a value, 08h, is guessed by software, and the io base of card #2 jump to 240h. because 240h is conflict with card #1, user can only access the value of asr butsignature. 6. software keep guessing and writing 1 to auto. the io base of card #2 change from 240h to 280h. 7. user can access signature and asr from this io base, the conflit_free io base for card #2 is found. note : mx98905 uses one byte (id byte #5) to determine sid is matched with hid or not, therefore, there is 1/256 posibility for 2 lan cards get hit simultaneously. out dx, al out dx,al out dx,al when this certain value "hits" the 5th network i.d. (the least significant byte), then io base of this "id hit" lan card will be locked by mx98905 itself. i.e when writting 1 to auto, the io base will not be changed. in case it is necessary for system to have more than one lan cards plugged, the mx98905 provides a powerful solution to resolve "multiple lan card io base conflict problem". it is not necessary for users to plug one lan into the system then configure the io base of the lan card; then remove the first lan card which is already configured and proceeds the second lan card and so forth. using mx98905, user can plug mutiple lan cards into the system at the same time and then use software to configure these lan cards for themselves. to simply the mutiple lan card auto configuration's operation, the mx98905 provides a bit, multi, in the hcmr. when this bit is set to 1, all lan cards which use mx98905 will be forced to change to io map (i.e. novell ne2000 compaible). the "id guess state machine" inside the mx98905 will be enables after multi bit is enabled. after that, software can write a certain value (will be explained in more detail in the following sub_ section) into the mx98905 by consecutive 4 write to port 378h. the following shows an example (in 8088 assembly code) for writting this certain value into mx98905: mov dx, 378 mov al, certain_valuer out dx, al
25 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b the internal state machine will be reset after eeprom_store is finished. this algorithm is preliminary. for actual implementa- tion, user can contact with our fae by calling 886-02- 7191977 for details. 10. twisted-pair interface (tpi) module the tpi has five main logical functions: 1. the smart squelch is responsible for determining when valid data is present on the differential re- ceive inputs rxip and rxim 2. the collision function checks for simultaneous transmission and reception of data on the txop, txom, rxip and rxim. 3. the link detector/generator checks the integrity of the cable connecting the two twisted-pair maus. 4. the jabber disables the transmitter if it attempts to transmit a longer-than-legal packet. 5. the tx driver & pre-emphasis transmit man- chester-encoded data to the twisted-pair network via the summing resistors and transformer/filter. 11. smart squelch to make sure that impulse noise on the receive inputs will not be mistaken for a valid signal, the enc carries out an intelligent receive squelch on the rx differential inputs. the squelch circuitry uses a mix of amplitude and timing measurements. smart squelch checks the signal at the start of packet and any pulses that do not exceed the squelch level, either positive or negative, depending on polarity, is rejected. after this first squelch level is overcome the opposite squelch level must be exceeded within 150 ns. finally, the signal goes beyond the original squelch level within a further 150 ns in order for the input waveform not to be rejected. the procedure entails the loss of at least three bits at the start of each packet. when these conditions are satisfied a control signal will be generated to show the remainder of the cir- cuitry that valid data is present. then the smart squelch circuitry is reset. valid data is deemed present until either squelch level has not been generated for a time longer than 150 ns, which shows end of packet. if good data is detected, the squelch levels are reduced to contain the noise effect which may lead to premature end- of-packet detection. 12. collision a collision is detected by the tpi module when the receive and transmit channels are active simultane- ously. if the tpi is receiving when a collision is detected it is reported to the controller immediately. if, however, the tpi is transmitting when a collision is detected the collision is not reported until seven bits have been received while in the collision state. this prevents a collision from being reported incorrectly due to noise on the network. the signal to the controller remains for the duration of the collision. approximately 1 m s after the transmission of each packet a signal called the signal quality error (sqe) consisting of typically 10 cycles of 10 mhz is gener- ated. this 10 mhz signal, also called the heartbeat, ensures the continued functioning of the collision cir- cuitry. 13. link detector/generator this is a timer circuit that generates a link pulse as shown in the 10base-t specification. with a width of 100 ns, the pulse is transmitted every 16 ms on the txo+ output in the absence of transmit data. the pulse checks the integrity of the connection to the remote mau, and the link detection circuit checks for valid pulses from the remote mau. the link detector will disable the transmit, receive, and collision detection functions if valid link pulses are not received. to determine that a good twisted-pair link exists, the gdlnk output directly drives an led; the led will be on during normal conditions.
26 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 14. jabber whenever the transmitter is active for greater than 52 ms, the jabber timer monitors the transmitter and disables the transmission. in this case, the transmitter is then disabled for the time that endec modules internal transmit enable is asserted. this signal has to be deasserted for about 750 ms before the jabber re-enables the transmit outputs. 15. transmit driver the transmitter has four signals, the true and com- plement manchester-encoded data (txop and txom). these signals may be delayed by 50 ns (txodp and txodm). these four signals are combined, txop with txodm and txom with txodp. known as digital pre-emphasis, this process is required to compensate for the twisted-pair cable which acts like a low-pass filter and can greatly weaken the 10 mhz (50 ns) pulses of the manchester-encoded waveform than the 5 mhz (100 ns) pulses. a combination of these signals is shown below: data pattern 110011 txop txodm combined waveform with pre-emphasis seven consecutive link pulses or three consecutive link pulses having reversed polarity are detected. a wiring error at either end of the tpi cable can cause polarity reversal. upon detection of this reversal the condition is latched and pol is asserted. correcting this error is the tp1 and will also decode received data correctly, thus getting rid of the need to check the wiring error. 17. manchester encoder and differential driver on the transformers secondary, the differential trans- mit pair drives up to 50 meters of twisted-pair aui cable. these outputs are source followers requiring two 270 w pulldown resistors to ground. 18. manchester decoder this decoder is composed of a differential receiver and a pll to separate a manchester-decoded data stream into internal clocks signals and data. when using the standard 78 w transceiver drop cable, see that the dif- ferential input must be externally terminated with two 39 w resistors connected in series. these resistors are optional in thin ethernet applications. a squelch circuit at the input rejects signals with levels less than - 175 mv to prevent noise from triggering the decoder. and signals negative than -300 mv are decoded; data becomes valid within 5 bit times. the mx98905 may be able to take bit jitter up to 18 ns in the data that is received. 19. collision translator if the ethernet transceiver, when in aui mode, detects a collision, it generates a 10 mhz signal to the differen- tial collision inputs (cdp and cdm) of the mx98905. when these inputs are active, the mx98905 uses this signal to cancel its current transmission and resched- ule another one. the collision differential inputs are ended in the same way as the differential receive inputs. the squelch circuitry is also similar, rejecting pulses with levels less than -175 mv. 20. receive deserializer the receive deserializer starts to work when the input 16. status information this information is shown at the enc on the crs/rx, txe/tx, col and pol outputs as decribed in the pin description table. these outputs can drive status leds by means of an appropriate driver circuit. normally low, the pol output will be driven high when
27 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b signal carrier sense is asserted. it allows incoming bits to be shifted into the shift register by the receive clock provided by the snc (serial network converter). the serial receive data is also routed to the crc generator/checker to detect crc code. the receive deserializer includes a synch detector that detects the sfd (start of frame delimiter) to establish where byte boundaries within the serial bit stream are located, i.e., when a 1,1 bit sequence is detected, it begins to collect data. after every eight receive clocks, the byte-wide data is transferred to the 16-byte fifo (two 8-byte fifos) alternatively and the receive byte count is incremented. the first six bytes after the sfd are checked for valid comparison by the address recognition logic. if the address recognition logic does not recognize the packet, the fifo is cleared. 21. address recognition logic the address recognition logic compares the destina- tion address field (first 6 bytes of the received packet) with the physical address registers stored in the address register array, one byte at a time, by the 8th receive clock. if any one of the six bytes does not match the pre-programmed physical address, the protocol pla rejects the packet. this means that the packet does not belong to the node. all multicast destination addresses are filtered using a hashing technique by latching the 6 most significant bits of the crc generator. if the multicast address indexes a bit that has been set in the filter bit array of the multicast address register array, the packet is accepted. otherwise, it is rejected by the protocol pla. each destination address is also checked for all 1s, which is the reserved broadcast address. 22. packet transmission a complete transmit packet consists of preamble, synch, data, and crc fields. the data field is a contiguous assembled packet of destination address. source address, length field, and data with the format are shown below. during transmit, page start address register (tpsr) and the transmit byte count registers (tbcr0,1), control the dma transfer. as a transmit command is issued to enc, the packet of data in buffer memory pointed 0 by these registers will be moved into the fifo. the enc will generate and append the preamble, synch and crc fields. in addition, if transmitting data is smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. the programmer is responsible for adding and stripping pad bytes. general transmit packet format preamble synch destination address source address type length data pad (if data < 46 bytes) crc 62 bits 2 bits 6 bytes 6 bytes 2 bytes > 46 bytes 4 bytes tx byte count (tbcr 0, 1) 23. conditions required to begin trans- mission to initiate transmission of a packet, the tpsr (transmit page start register) and tbcr0, tbcr1 (transmit byte count registers) must be initialized and the txp bit in the command register must be set. the enc will start to prefetch transmit data from memory, if no reception is currently receiving. three conditions must be met before transmission: 1. the interframe gap timer has timed out the first 6.4 m s of the interframe gap. 2. at least one byte has entered the fifo, which means that burst transfer has begun. 3. if collision occurs in the enc, the backoff timer must expire before retransmit. if carrier sense is asserted before a byte has been loaded into the fifo, the enc will become a receiver.
28 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 24. collision recovery if transmission has collided with another station, the buffer management logic, which monitors the transmit circuitry will reset the fifo and restore the transmit dma pointers for retransmission of the packet. when collision is detected, the col bit in tsr will be set and the ncr (number of collisions register) will be incremented. if each of the 15 retransmissions results in a collision, the transmission will be terminated and the abt bit in the tsr will be set. if excessive collisions (i.e., 16 consecutive collisions) are encountered, ncr reads as zeros and transmission is aborted. 25. transmit packet assembly format the following diagrams show the format for assem- bling packets before they are transmitted for different byte- ordering schemes. the various formats are selected in the data configuration register. da = destination address sa = source address t/l = type/length field da1 da3 da5 sa1 sa3 sa5 t/t1 data1 da0 da2 da4 sa0 sa2 sa6 t/l0 data0 bit d15 d8 d7 d0 bos = 0, wts -1 in data configuration register. this format used with series 32000, 808x-type processors. da0 da2 da4 sa0 sa2 sa4 t/l0 data0 da1 da3 da5 sa1 sa3 sa5 t/l1 data1 bit d15 d8 d7 d0 bos = 1, wts = 1 in data configuration register. this format is used with 68000-type processors.
29 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b da0 da1 da2 da3 da4 da5 sa0 sa1 sa2 sa3 bos = 0, wts = 1 in data configuration register. this format is used with general 8-bit cpus.
30 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 26. physical address registers (par0- par5) the physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. it compares physical addresses in par0-par5 with incoming data one byte at a time. the bit assignment shown below relates the sequence in par0-par5 to the bit sequence of the received packet. d7 d6 d5 d4 d3 d2 d1 d0 par0 da7 da6 da5 da4 da3 da2 da1 da0 par1 da15 da14 da13 da12 da11 da10 da9 da8 par2 da23 da22 da21 da20 da19 da18 da17 da16 par3 da31 da30 da29 da28 da27 da26 da25 da24 par4 da39 da38 da37 da36 da35 da34 da33 da32 par5 da47 da46 da45 da44 da43 da42 da41 da40 destination address source p/s da0 da1 da2 da3 .......... da46 da47 sa0 .......... note: p/s = preamble, synch da0 = physical/multicast bit
31 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b register address mapping command register address decode swr# srd# cs# ra0-ra3 command page 0 (read) ps1, ps0 command page 1 (read) command page 2 (read) command test page command page 0 (write) command page 1 (write) command page 2 (write) command test page
32 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 27. direct memory access control (dma) the dma capabilities of the enc greatly simplify use of the mx98905 in typical configuration. the local dma channel transfers data between fifo, which is inside the enc, and memory which is outside the enc. there are two kinds of local dma type: local dma read and local dma write. local dma read moves data from memory into fifo on transmission. should a collision occur (up to 15 times), the packet is retransmitted with no processor intervention. local dma write transfers data from fifo to memory on reception. a remote dma channel is also provided on the enc to accomplish transfers between a buffer memory and a system memory whenever the i/o map board design is required. the two dma channels (local dma and remote dma) can alternatively be combined to form a single 32-bit address with 8- or 16-bit data. 28. dual dma configuration network activity is isolated on a local bus, where the enc's local dma channel performs burst transfers between the buffer ring and the enc's fifo. the remote dma transfers data between the buffer ring and the host memory by means of a bi-directional i/o port. meanwhile, remote dma provides local addressing capability and is used as a slave dma by the host. host side addressing must be provided by a host dma or the cpu. the enc allows local and remote dma operations to be interleaved because the enc takes care of the bus arbitration problem itself. 29. internal registers all internal registers are mapped into three pages and selected by two bits, ps1 and ps0, of command register. input pins ra0-ra3 are used to address these internal registers which are 8-bit wide and are commonly accessed during enc register read/write operation. for user's convenience, registers that are commonly accessed during enc operation are mapped into page 0. page 1 registers are used primarily for initialization while page 2 registers are used for diagnostics. partitioned registers make one write/read cycle possible for accessing those commonly used registers.
33 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b register descriptions 1. enhanced feature new page register address assignment new page 1 address assignment for i/o map sa00..3 read write 00h reserved reserved 01h reserved reserved 02h reserved reserved 03h reserved reserved 04h reserved reserved 05h reserved reserved 06h reserved reserved 07h reserved reserved 08h signature (x, 78h) reserved 09h hidden config. (hcfr) hidden config. (hcfr) 0ah hidden command (hcmr) hidden command (hcmr) 0bh reserved reserved 0ch configuration c (cc) configuration c (cc) 0dh reserved reserved 0eh autostatus reg. (asr) reserved 0fh reserved reserved
34 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b new page 1 address assignment for memory map sa0..4 read write 10h reserved reserved 11h reserved reserved 12h reserved reserved 13h reserved reserved 14h reserved reserved 15h reserved reserved 16h reserved reserved 17h reserved reserved 18h signature (x, 78h) reserved 19h hidden config. (hcfr) hidden config. (hcfr) 1ah hidden command (hcmr) hidden command (hcmr) 1bh reserved reserved 1ch configuration c (cc) configuration c (cc) 1dh reserved reserved 1eh autostatus reg. (asr) reserved 1fh reserved reserved
35 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b data transfer ports and reset port are always acces- sible no matter what the value of npgen and pgsel is in i/o map design. 2. enhanced feature registers 2.1 hidden command register (r/w) (hcmr) this register controls all the functions provided in enhanced mode. it can always be accessed by con- secutive 2 writes to port 278h, followed by 2 consecutive 2 writes to port 378h, i.e., write ports : 278h ? 278h ? 378h ? 378h (when i/o base not sure) after the i/o base is determined (see functional de- scription), this register can be accessed by one i/o instruction using the address assignment shown in provious section. note: don't write this register through base+0ah/ base+1ah (i/o/mem) except it is confirmed that i/o base does not conflict with other add_on card. 0 bits hcfre pgsel npgen auto idwcmd allwr multi resvd 1 2 3 4 5 6 7
36 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b symbol bit description hcfre d0 register hcfre enable. power on low. 0 : disable hcfr. 1 : enable hcfr. when user issues eestore in configuration register b, contents in figh byte of ofh of eeprom. whcih is reserved at npgen,pgsel d2,d1 new page enable/page select. power on low. 0x: normal mode. user can access controller's internal registers. 10 : user can access idprom through iobase + 00..ofh in i/o map. see table 4 for your reference. 11: new page 1 selectsd. user can access hcmr, cc, asr and signature. see "new page 1 address assignment for i/o map" and "new page 1 address assignment for memory map " for more detail information. make sure set npgen to 0 before normal operation. data port and reset port in i/o map are accessible no matter what the value of npgen and pgsel are. auto d3 auto jump to next i/o base. power on low. 0 : write a 0 to this bit has no effect.1 : write an 1 to this bit will cause i/o base auto jump follow the sequence described in section 9.5- - auto configuration. in multiple lan cards auto configuration's application (see section 9.5), if sid hits the hid, then write an 1 to this bit has no effect. the first time writing an 1 to auto will cause io base change to 300h no matter what the current io base is. whenever auto is issued, the value of ioad2..0 in ca and page in hcfr will be updated automatically by the state machine inside the mx98905. either 7 or 15 io bases should be determined before auto is issued to prevent the internal state machine getting confused. any iordl signal activates will reset this bit. idwcmd d4 idprom write command. power on low. 0 : write a 0 to this bit has no effect. 1 : the mx98905 will write the first 4 words of prom data (net work i.d., boardtype and checksum) back to eeprom when this bit is set. when the operation is completed, this bit will be reset by mx98905 itself. don't write an 1 to this bit and eestore of cb simultaneously, this will cause internal state machine malfunction. allwr d5 write ca, cb, cc, hcfr, the entire prom content back to eeprom. power on low. 0 : only ca, cb, cc and hcfr are written back to eeprom when eestore bit of cb is set to 1. 1 : ca, cb, cc, hcfr, and the entire prom content will be writtenback to eeprom when eestore bit is set to 1. if new network i.d. is necessary, make sure i.d. is updated before this bitCis set and before eestore bit is set to1, the following write sequence will be followed after eestore bit is set to 1, ca, cb -> cc, hcfr -> ido, idi -> id2, id3 -> id4, id5 -> and the rest of the content in prom. hidden command register (r/w) (hcmr)
37 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b symbol bit description multi d6 enable multiple lan card auto configuration 0 : disable consecutive 4 writes to port 378h (sid buffer) . 1 : the mx98905 will be forced to i/o map, i.e. memio of ca will be forced to zero. consecutive 4 writes to port 378h will be enabled. when a 0 is written to this bit, the mx98905 will change to its original mode (i/o or memory). resvd d7 reserved. power on low. note : hcmr can always be accessed by writing to port 278h and 378h(follow the certain sequence de- scribed above). remember not to access this register through direct io access unitl a conflict _free i/o base is found. 2.2 hidden configuration register (r/w) (hcfr) this register controls all the functions provided in enhanced mode. it can always be accessed by con- secutive 2 writes to port 278h, followed by 2 consecutive 2 writes to port 378h, i.e., write ports : 278h ? 278h ? 378h ? 378h (when i/o base not sure) after the i/o base is determined (see functional de- scription), this register can be accessed by one i/o instruction using the address assignment shown in provious section. note: don't write this register through base+0ah/ base+1ah (i/o/mem) except it is confirmed that i/o base does not conflict with other add_on card. ioben page newcf locke 0 1 2 3 4 x 5 x 6 x 7 x bits hidden command register (r/w) (hcmr)(continued)
38 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b these four bits (ioben, page, newcf and locke) can be loaded/stored from/to eeprom. resv4..1 --- reserved bits for future use. note: don't write this register through base+09h/ base+19h except it is confirmed that i/o base does not conflict with other add_on card. symbol bit description ioben d0 i/o base enable. power-on low 0 : 7 i/o base (compatible with dp83905) 1 : 15 i/o bases page d1 page select for i/o base. power-on low only valid when ioben and hcfre of hcmr is high 0 : i/o base address are the same as ioad2..0 of configuration a 1 : i/o base address are redefined (see i/o base support for more detail). this bit will be updated automatically according to the sequence of auto configuration when ioben is set. newcf d2 new configuration loaded to ca, cb and cc after eestore is executed. power-on low 0 : new configuration will not be loaded to ca, cb and cc after eestore algorithm is executed. compatible with dp83905. 1 : new configuration will be loaded to ca, cb and cc after eestore algorithm is completed. enhanced feature. locke d3 lock enable. i/o base will not be changed when auto of hcmr is written into. power-on low. 0 : enable internal lock bit. write 1 to auto will change i/o base 1 : enable internal lock bit. write 1 to auto will not change i/o base. when this bit is set, auto of hcmr has no effect. user cannot read the value of signature register. after i/o base is determined (see multi_lan card conflict free for more detail), this bit should be programmed through base+09h for i/o map or base+19h for shared memory map. 2.2 hidden configuration register (r/w) (hcfr)(continued)
39 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 2.3 signature for multi_board auto con- figuration (r) (sgn) this register is only used in multi_lan card auto configuration. it is readable only when the lsb of network id programmed by user is matched with the contents of id5 of prom. ? read port : base + 08h/base + 18h (i/o/ mem) ? read condition npgen = 1 pgsel = 1 ? the value of signature is 78h (ascii code for 'x') note : lock status will be reset after user has read the value of signature. user should exactly follow the algorithm provided in enhanced feature description for multi_board lan card auto configuration. for user's convenience, we strongly recommend that he issues eestore after auto configuration is done. 2.5 autostatus register (r) (asr) ? read port : base + 0eh/base + 1eh (i/o/ mem) ? read condition : npgen = 1 pgsel = 1 when 7 i/o bases are selected, the following value sequence will be shown on asr whenever auto of hcmr is written into: 18 ? 22 ? 34 ? 46 ? 59 ? 6a ? 0b when 15 i/o bases are enabled, the following sequence is available: 18 ? 22 ? 34 ? 46 ? 59 ? 6a ? 7b ? 8c ? 9d ? ae ? bf ? c0 ? d1 ? e5 ? 07 i.e., when auto is first written, the contents of asr are 18h; if user writes auto again, the value of asr changes from 18h to 22h, etc. this feature can be used in auto configuration to determine whether the i/ o base of the lan card is in conflict with the others. iob5 iob6 iob7 iob8 auty0 auty1 auty2 auty3 0 1 2 3 4 5 6 7 bits iob8..5 : i/o base bit 8 to bit 5. auty3..0 : states for auto configuration state machine.
40 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 3. configuration registers 3.1 configuration register a (r/w) (ca) this register can be accessed by reading 0ah of internal page 0 register followed by writing to that address. if other read/write takes place between the read and the write, then write to 0ah will access the remote byte count register 0. ioad0 ioda1 ioad2 int0 int1 int2 fread memio 0 1 2 3 4 5 6 7 bits symbol bit description ioad2-0 d0-d2 i/o address. these three bits determine the base i/o address of the mx98905 controller when enhanced mode is disabled (npgen of hcmr is low). when the enhanced mode is enabled, the base i/o address will be determined by 5 bits, which are ioad2-0 of ca, npgen and pgsel of hcmr. see i/o base determination for details. int2-0 d3-d5 interrupt line used. two interrupt modes are supported by the mx98905, which can be enabled by setting intmod of configuration c. direct drive mode : in this mode, an interupt output pin will be driven active on a valid interrupt condition (see isr for more detail). only one pin is driven in this mode depending on the following condition, the other three will remain tri-state. int2 int1 int0 interupt x 0 0 int0 x 0 1 int1 x 1 0 int2 x 1 1 int3 code output mode : int3 is the active interrupt output while pins int0-int2 are programmable outputs reflecting the values on bits 3 to 5, i.e., when bits 3 and 4 of ca is high, then int0, int1 and int3 are driven.
41 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 3.1 configuration registers a (r/w) (ca) (continued) symbol bit description fread d6 fast read. when this bit is set, the mx98905, in i/o mode, will begin next port fetch before system finishes reading the current data in data port. in slow isa system, programming this bit may cause data corrupt in data port. memio d7 memory or i/o mode. when this bit is set to 0, i/o mode is selected. when it is set high, it is in shared memory mode.
42 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 3.2 configuration register b (r/w) (cb) this register can be accessed by reading 0bh of internal page 0 register followed by writing to that address. if other read/write takes place between the read and the write, then write to 0bh will access the remote byte count register 1. when loading from eeprom during power-on reset, note that the value of eestore is always 0, i.e., the value of eestore can only be changed during register write operation. phys0 phys1 gdlink io16con chanrdy be bpwr eestrore 0 1 2 3 4 5 6 7 bits symbol bit description phys0-1 d0-d1 physical layer interface. phys1 phys0 interfadce 0 0 tpi (10base-t compatible squelch level) 0 1 thin ethernet (10base2, thin pin high) 1 0 thick ethernet (10base5, aui port) 1 1 tpi (reduced squelch level) the thin pin can be used to enable the dc-dc converter required by 10base2 specification to provide electrical isolation. gdlink d2 good link. there are different definitions for this bit in write and read modes. write mode : write 1 to this bit will disable the link pulse integrity test. read mode : when this bit is read, it indicates the link status, reflecting the value shown on the gdlinkl led. 0 : a. the mx98905 is in aui mode b. the mx98905 is in tpi mode, link enable, link bad 1 : a. link disable b. the mx98905 is in tpi mode, link enable, link good
43 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 31 configuration register b (r/w) (cb) (continued) symbol bit description io16con d3 io16l control. when this bit is set low, io16l is generated only on address decode. when it is high, the mx98905 will generate io16l after iordl, or iowrl go active. chanrd d4 chrdy from iordl or iowrl or from bale. when this bit is set low, the mx98905 will generate chrdy after the command strobe. when it is high, chrdy will be generated by the mx98905 after bale goes high. be d5 bus error. this bit shows that the mx98905 has detected a bus error (the mx98905 attempts to insert wait state into a system access and the system terminates the cycle without monitoring the wait state). writing a one to this bit clears it to zero, but writing a zero to this bit has no effect. bpwr d6 boot prom write. write cycles will be generated to the boot prom only when this bit is set high. eestore d7 eeprom store. writing a one to this bit enables the eeprom store algorithm, as mentioned. this bit should not be configured to high either from switches or from an eeprom. note that this bit and idwcmd of hcmr can't be set high simultane- ously to prevent crashing the internal state machine of the mx98905.
44 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b bps0 bps1 bps2 bps3 comp intmod clksel sofen 0 1 2 3 4 5 6 7 bits symbol bit description bps0-3 d0-d3 boot prom select. selects address and the size with which boot prom begins. when the system reads within the selected memory area, the mx98905 reads the data in through memd0-7 and drives it onto the system data bus. the following are valid addresses and size provided by the mx98905: bps3 bps2 bps1 bps0 address size (i/o shared memory) 0 0 0 x x no boot prom 0 0 1 0 0c000h 8k/16k 0 0 1 1 0c400h 8k/16k 0 1 0 0 0c800h 8k/16k 0 1 0 1 0cc00h 8k/16k 0 1 1 0 0d000h 8k/16k 0 1 1 1 0d400h 8k/16k 1 0 0 0 0d800h 8k/16k 1 0 0 1 0dc00h 8k/16k 1 0 1 0 0c000h 32k/32k 1 0 1 1 0c800h 32k/32k 1 1 0 0 0d000h 32k/32k 1 1 0 1 0d800h 32k/32k 1 1 1 0 0c000h 64k/64k 1 1 1 1 0d000h 64k/64k 3.3 hardware configuration register c (cc) access to configuration register c is allowed only in the mx98905 enhanced mode. this feature is not supported when the mx98905 is not programmed to new page 1. ? read/write port : base + 0ch/base + 1ch (i/o/mem) ? read/write condition: npgen = 1 pgsel = 1
45 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 3.3 hardware configuration register c (cc) (continued) symbol bit description comp d4 compatible. when this bit is low, the mx98905 is compatible with the ethercard plus and novell ne2000 boards. in compatible mode, only 16 kbytes ram memory are accessible. when this bit is set high, full 64 kbytes of memory can be accessed. intmod d5 interrupt mode. when this bit is low, the mx98905 is in direct drive interrupt mode. when it is high, coded output interrupt mode is selected. clksel d6 clock select. if this bit is high, the mx9890 core is clocked by the input bsclk pin. if it is low, the mx9890 core is clocked by the 20mhz clock from internal mcc module. sofen d7 software enable. 0 : user can program configuration register a and b in software. 1 : ca and cb are not accessible.
46 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 4. shared memory mode control registers 4.1 shared memory at detect regsiter (r) atdet 0 1 x 2 x 3 x r x 5 x 6 x 7 x bits symbol bit description atdet d0 at detect. this bit shows the value on the atxt pin and can be accessed by software to determine whether the mx98905 is operating in an 8- or 16-bit slot. when this bit is high, the mx98905 is operating in a 16-bit slot.
47 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 4.2 shared memory control register 1 (c1) 0 bits a13 a14 a15 a16 a17 a18 meme reset 1 2 3 4 5 6 7 symbol bit description a13-18 d0-d5 a13 to a18. lower part of the address register used to determine the position of the memory of the mx98905 within the system memory map. meme d6 memory enable. enables external memory accesses when held high. power- on low. to enable the memory into the system's memory map, the user must program the base memory address and set this bit high. reset d7 resets. resets the mx9890 core of the mx98905 controller.
48 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 4.3 shared memory control register 2 (c2) 0 bits la23 la23 la23 la23 la23 unused memw en16 1 2 3 4 5 6 7 symbol bit description la19-23 d0-d4 la19 to la23. upper part of the address register used to determine the position of the memory of the mx98905 within the system memory map. memw d6 memory width. sets width of external memory. when this bit is set high, external memory is accessed as word wide, i.e., in compatible mode, 16 kbytes are available and 64 kbytes are available in noncompatible mode (only when en16 is set high also). when it is low, external memory is accessed as byte wide, so only 8 kbytes of memory are available in compatible mode and 32 kbytes of memory are available in noncompatible mode. en16 d7 enable 16 bit. allow 16-bit system accesses to external memory when it is high. m16l output will be generated in this mode. when low, only 8-bit accesses are allowed, and m16l will stay high.
49 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 5. command register(cr) 00h (read/write) the command register is used to take the controller on/ offline (sta and stp bits), initiate transmissions (txp bit), enable or disable remote dma operations (rd2, rd1 and rd0 bits), and select register pages (ps1 and ps0). to issue a command, the microprocessor sets the corresponding bit(s). in addition, commands may be overlapped following the guidelines below: 1. if a remote dma operation overlaps a transmission, rd0, rd1 and rd2 must be written with the desired values, and a "0" or "1" may be written to the txp bit, because writing a "0" to txp has no effect after transmission is activated. 2. a remote write dma may not overlap remote read operation and vice versa. each operation must either be completed or aborted before starting the other one. 3. if a transmit command overlaps with a remote dma operation, bits rd2, rd1 and rd0 must be maintained for the remote dma command when setting the txp bit. note: if a remote dma command is reissued while giving the transmit command, the dma will complete the process immediately if the remote byte count registers (rbcr1 and rbcr0) have not been reinitialized, i.e., user has to program rbcr0 and/or rbcr1 every time he needs remote dma service. 4. bits ps1, ps0, rd2 and stp can be set at any moment. stp sta txp rd0 rd1 rd2 ps0 ps1 0 1 2 3 4 5 6 7 bits
50 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 5. command registers (continued) symbol bit description stp d0 stop : software reset command, takes the controller offline; no packets will be received or transmitted if this bit is set high. any reception or transmission in progress will enter the reset state after operation is completed. this bit must be cleared and the sta bit must be set high to exit the reset state. the software reset is executed only when the rst bit in the isr is set to 1. stp powers up high. note: if the enc has previously been in start mode and the stp is set, both the stp and sta bits will remain set. sta d1 start : this bit is used to activate the enc after either power-up, or when the enc has been placed in a reset mode by software command or error. sta powers up low. txp d2 transmit packet : this bit must be set to initiate transmission of a packet only after the transmit byte count (tbcr1 and tbcr0) and transmit page start register (tpsr) have been programmed. txp is internally reset either after the transmission is completed or aborted. pd0, pd1, d3, d4, d5 remote dma command : these three-encoded bits control operation of the remote dma channel. rd2 can be set to abort any remote dma command in progress. the remote byte count registers should be cleared by host whenever a remote dma has been aborted. the remote start addresses are not restored to the starting address if the remote dma is aborted. hence, for another remote dma operaton, host should provide a starting address for enc in order to operate correctly. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 send packet 1 x x abort/complete remote dma (note) ps0, ps1 d6, d7 page select : these two-encoded bits select which register page is to be accessed with addresses ra0-3 ps1 ps0 0 0 register page 0 0 1 register page 1 1 0 register page 2 1 1 reserved pd2
51 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 6. interrupt status register (isr) 07h (read/write) this register is accessed by the host processor to de- termine the cause of an interrupt. any interrupt can be masked in the interrupt mask register (imr). individ- ual interrupt bits are cleared by writing a "1" into the corresponding bit of the isr. the int signal is active as long as any unmasked signal is set; it will not go low until all unmasked bits in this register have been cleared. the isr must be cleared after power-up by writing it with all 1's. prx ptx rxe txe ovw cnt rdc rst 0 1 2 3 4 5 6 7 bits symbol bit description prx d0 packet received : indicates packet received with no errors. ptx d1 packet transmitted : indicates packet transmitted with no errors. rxe d2 receive error : indicates that a packet was received with one or more of the following errors: - crc error - frame alignment error - fifo overrun - missed packet txe d3 transmit error : set when packet is transmitted with one or more of the following errors: - excessive collisions - fifo underrun ovw d4 overwrite warning: set when receive buffer ring storage resources have been exhausted. (current pointer has reached boundary pointer)
52 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 6. interrupt status register (isr) 07h (read/write) (continued) symbol bit description cnt d5 counter overflow : set when msb of one or more of the network tally counters has been set. rdc d6 remote dma complete : set when remote dma operation has been completed. rst d7 reset status : set when enc enters reset state and cleared when a start command is issued to the cr. this bit is also set when a receive buffer ring overflow occurs and is cleared when one or more packets has been removed from the ring. writing to this bit has no effect. note: this bit does not generate any interrupt; it is merely a status indicator. 7. interrrupt mask register (imr) 0fh (write) the interrupt mask register is used to mask interrupts. each interrupt mask bit corresponds to a bit in the interrupt status register (isr). if an interrupt mask bit is set, an interrupt will be issued whenever the corre- sponding bit in the isr is set. if any bit in the imr is set low, an interrupt will not occur when the bit in the isr is set. the imr powers up all zeros. prxe ptxe rxee txee ovwe cnte rdce 0 1 2 3 4 5 6 7 x bits
53 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 7. interrupt mask register (imr) 0fh (write) (continued) symbol bit description prxe d0 packet received interrupt enable 0: disables interrupt when packet is received. 1: enables interrupt when packet is received. ptxe d1 packet transmitted interrupt enable 0: disables interrupt when packet is transmitted. 1: enables interrupt when packet is transmitted. rxee d2 receive error interrupt enable 0: disables interrupt when packet is received with error. 1: enables interrupt when packet is received with error. txee d3 transmit error interrupt enable 0: disables interrupt when packet transmission results in error. 1: enables interrupt when packet transmission results in error. ovwe d4 overwrite warning interrupt enable 0: disables interrupt when buffer management logic lacks sufficient buffers to store an incoming packet. 1: enables interrupt when buffer management logic lacks sufficient buffers to store an incoming packet. cnte d5 counter overflow interrupt enable 0: disables interrupt when msb of one or more of the network statistics counters has been set. 1: enables interrupt when msb of one or more of the network statistics counters has been set. rdce d6 dma complete interrupt enable 0: disables interrupt when remote dma transfer has been completed. 1: enables interrupt when remote dma transfer has been completed. reserved d7 reserved
54 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 8. data configuration register (dcr) 0eh (write) this register is used to program the enc for 8- or 16-bit memory interface, select normal or loopback operation, select byte ordering in 16-bit application, and establish fifo threshold. the dcr must be initialized prior to loading the remote byte count registers. las is set on power-up. wts bos las ls arm ft0 ft1 0 1 2 3 4 5 6 7 x bits symbol bit description wts d0 word transfer select 0: selects byte-wide dma transfers 1: selects word-wide dma transfers wts establishes byte or word transfer for both remote and local dma transfers. note: when word-wide mode is selected, up to 32k words are addressable; a0 remains low. bos d1 byte order select 0: ms byte placed on ad15-ad8 and ls byte on ad7-ad0 (32000, 8086) 1: ms byte placed on ad7-ad0 and ls byte on ad15-ad8 (68000); ignored when wts is low. las d2 long address select 0: dual 16-bit dma mode 1: single 32-bit dma mode when las is high, the contents of the remote dma registers rsar0, 1 are issued as a16-a31. power-up high.
55 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 9. data configuration register (dcr) 0eh (write) (continued) symbol bit description ls d3 loopback select 0: loopback mode select. bits lb0, lb1 o f the tcr must be programmed for loopback operation. 1: normal operation. ignore the values of lb1 and lb0 of tcr. arm d4 auto-initialize remote 0: send command not executed, all packets removed from buffer ring under program control. 1: send command executed, remote dma auto-initialize to remove packets from buffer ring note: send command cannot be used with 68000-type processors and should be issued right after reception of packet is completed. ft0, ft1 d5,d6 fifo threshold select : encoded fifo threshold; establishes point at which bus is requested when filling or emptying the fifo. during reception, the fifo threshold indicates the number of bytes (or words) the fifo has filled serially from the network. during transmission, the fifo threshold indicates the number of bytes (or words ) the fifo has filled from the local dma. thus, the transmission threshold is 16 bytes less than the received threshold. note: fifo threshold setting determines the local dma burst length. receive thresholds ft1 ft0 word wide byte wide 0 0 1 word 2 bytes 0 1 2 words 4 bytes 1 0 4 words 8 bytes 1 1 6 words 12 bytes
56 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 10. transmit configuration register (tcr) 0dh (write) before transmission of a packet on the network, the transmit configuration register is configured to estab- lish the actions of the transmitter section of the enc during transmission of a packet on the network. lb1 and lb0 select loopback mode power-up as 0. crc lb0 lb1 atd ofst 0 1 2 3 4 5 x 6 x 7 x bits symbol bit description crc d0 inhibit crc 0: crc appended by transmitter 1: crc inhibited by transmitter in loopback mode crc can be enabled or disabled to test the crc logic. lb0, lb1 d1, d2 encoded loopback control : the type of loopback to be performed is determined by the following encoded bits. lb1 lb2 mode 0 0 0 normal operation mode 1 0 1 internal loopback mode 2 1 0 external loopback to sni mode 3 1 1 external loopback to tp atd d3 auto transmit disable : setting this bit allows another station to disable the enc's transmitter by transmission of a particular multicast packet. the transmitter can be re-enabled by resetting this bit, or by reception of a second particular multicast packet. 0: normal operation 1: reception of multicast address hashing to bit 62 disables transmitter; reception of multicast address hashing to bit 63 enables transmitter.
57 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 11 transmit configuration register (tcr) 0dh (write) (continued) symbol bit description ofst d4 collision offset enable : this bit modifies the backoff algorithm to allow prioritization of modes. 0: normal backoff algorithm 1: forces backoff algorithm modification to 0 to 2 min (3+n, 10) slot times for first three collisions, then follows standard backoff.( for first three collisions station has higher average backoff delay making a low-priority mode.) reserved d5 reserved reserved d6 reserved reserved d7 reserved 12. transmit status register (tsr) 04h (read) each particular bit of this register is set when the corre- sponding event occurs on the media during transmission of a packet. the contents of this register are not specified until after the first transmission and are cleared upon the start of the next transmission initiated by the host. a read of this register is necessary after each transmission. rtx col abt crs fu cdh owc 0 1 x 2 3 4 5 6 7 bits
58 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 12. transmit status register (tsr) 04h (read) (continued) symbol bit description ptx d0 packet transmitted : set when transmitted without error. (no excessive collisions or fifo underrun) (abt = "0", fu = "0") d1 reserved col d2 transmit collided: set when transmission collided at least once with another station on the network. the number of collisions is recorded in the number of collisions registers (ncr). abt d3 transmit aborted : set when transmission is aborted because of excessive collisions. (total number of transmission attempts equals 16). crs d4 carrier sense lost : set when carrier is lost during transmission of a packet. carrier sense is monitored from the end of preamble/synch until txen is dropped. note that transmission is not aborted on loss of carrier. fu d5 fifo underrun : set when enc cannot gain access of the bus before the fifo empties. transmission of the packet will be aborted. cdh d6 cd heartbeat : set when the transceiver fails to issue a collision signal after transmission of a packet. the collision detect (cd) heartbeat signal must com- mence during the first 6.4 m s of the interframe gap following a transmission. in some collisions, however, the cd heartbeat bit will be set even when the trans- ceiver is not performing the cd heartbeat test. owc d7 out-of-window collision : set when a collision occurred after a slot time (51.2 m s). transmission will not be aborted.
59 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 13. receive configuration register (rcr) 0ch (write) this register determines what types of packets to be accepted and what mode the enc will be in. the types include address type and error type. in the error type, when any one bit of sep and ar is clear and the packet received matches the condition set in sep or ar, the packet is rejected. sep ar ab am pro mon 0 1 2 3 4 5 6 x 7 x bits symbol bit description sep d0 save error packets. 0: packets with crc and frame alignment errors are rejected. 1: packets with crc and frame alignment errors are accepted. ar d1 accept runt packets : this bit allows the receiver to accept packets that are smaller than 64 bytes. the packet must be at least 8 bytes long to be accepted as a runt. 0: packets with fewer than 64 bytes rejected. 1: packets with fewer than 64 bytes accepted. ab d2 accept broadcast : enables the receiver to accept a packet with an all 1's destination address. 0: packets with broadcast destination address rejected. 1: packets with broadcast destination address accepted. am d3 accept multicast : enables the receiver to accept a packet with a multicast address; all multicast addresses must pass the hashing array. 0: packets with multicast destination address not checked. 1: packets with multicast destination address checked.
60 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 13. receive configuration register (rcr) 0ch (write) symbol bit description pro d4 promiscuous physical: enables the receiver to accept all packets with a physical address. 0: physical address of mode must match the station address programmed in par0- par5. 1: all packets with physical addresses accepted. mon d5 monitor mode : enables the receiver to check addresses and crc on incoming packets without buffering to memory. the missed packet tally counter will be incremented for each recognized packet. 0: packets buffered to memory. 1: packets checked for address match, good crc and frame alignment but not buffered to memory. reserved d6 reserved reserved d7 reserved n ote: d2 and d3 are "or'd" together, i.e., if d2 and d3 are set the enc will accept broadcast and multicast addresses as well as its own physical address. to establish full promiscuous mode, bits d2, d3 and d4 should be set. in addition, the multicast hashing array must be set to all 1's in order to accept all multicast addresses.
61 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 14. receive status register (rsr) 0ch (read) this register records status of the received packet. it includes information on errors, the type of address match, either physical or multicast, and the aborted packet type. the contents of this register are written to buffer memory by the dma after receiving a good packet. if packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet, when an erroneous packet is received. if packets with errors are to be rejected the rsr will not be written to memory. the contents will be cleared when the next packet arrives. crc errors, frame alignment errors and missed packets are counted internally by the enc, which relinquishes the host from reading the rsr in real time to record errors for network management functions. the contents of this register are not specified until after the first reception. prx crc fae fo mpa phy dis dfr 0 1 2 3 4 5 6 7 bits symbol bit description prx d0 packet received correctly : indicates packet received without error. (bits crc, fae, fo and mpa are zero for the received packet.) set when packets are received complete. crc d1 crc error : indicates packet received with crc error. increments tally counter (cntr1). this bit will also be set for frame alignment errors. set when packets are received complete. fae d2 frame alignment error : indicates that the incoming packet did not end on a byte boundary and the crc did not match at last byte boundary. increments tally counter (cntr0). set when packets are received complete. fo d3 fifo overrun: this bit is set when the fifo is not serviced causing overflow during reception. reception of the packet will be aborted. mpa d4 missed packet : set when packet intended for node cannot be accepted by enc because of a lack of receive buffers, or if the controller is in monitor mode and did not buffer the packet to memory increments tally counter (cntr2).
62 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 14. receive status register (rsr) 0ch (read) (continued) symbol bit description phy d5 physical/multicast address : indicates whether received packet has a physical or multicast address type. set/reset when destination address has been received. 0: physical address match 1: multicast/ broadcast address match dis d6 receiver disabled: set when receiver is disabled by entering monitor mode. reset when receiver is re-enabled when exiting the monitor mode. dfr d7 deferring : set when crs or col inputs are active. if the transceiver has asserted the cd line as a result of the jabber, this bit will stay set indicating the jabber condition. note: the following coding applies to crc and fae bits fae crc type of error 0 0 no error (good crc and < 5 dribble bits) 0 1 crc error 1 0 illegal, will not occur 1 1 frame alignment error and crc error
63 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 15. register address assignments (continued) page 0 address assignments (ps1 = 0, ps0 = 0) ra3-ra0 read write 00h command register (cr) command register (cr) 01h current local dma address 0 (clda0) page start register (pstart) 02h current local dma address 1 (clda1) page stop register (pstop) 03h boundary pointer (bnry) boundary pointer (bnry) 04h transmit status register (tsr) transmit page start address (tpsr) 05h number of collisions register (ncr) transmit byte count register 0 (tbcr0) 06h fifo (fifo) transmit byte count register 1 (tbcr1) 07h interrupt status register (isr) interrupt status register (isr) 08h current remote dma address 0 (crda0) remote start address register 0 (rsar0) 09h current remote dma address 1 (crda1) remote start address register 1 (rsar1) 0ah reserved remote byte count register 0 (rbcr0) 0bh reserved remote byte count register 1 (rbcr1) 0ch receive status register (rsr) receive configuration register (rcr) 0dh tally counter 0 (frame alignment error) transmit configuration register (tcr) (cntr0) 0eh tally counter 1 (crc error) (cntr1) data configuration register (dcr) 0fh tally counter 2 (missed packet error) interrupt mask register (imr) (entr2)
64 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 15. register address assignments (continued) page 1 address assignments (ps1 = 0, ps0 = 1) ra3-ra0 read write 00h command register (cr) command register (cr) 01h physical address register 0 (par0) physical address register 0 (par0) 02h physical address register 1 (par1) physical address register 1 (par1) 03h physical address register 2 (par2) physical address register 2 (par2) 04h physical address register 3 (par3) physical address register 3 (par3) 05h physical address register 4 (par4) physical address register 4 (par4) 06h physical address register 5 (par5) physical address register 5 (par5) 07h current page register (curr) current page register (curr) 08h multicast address register 0 (mar0) multicast address register 0 (mar0) 09h multicast address register 1 (mar1) multicast address register 1 (mar1) 0ah multicast address register 2 (mar2) multicast address register 2 (mar2) 0bh multicast address register 3 (mar3) multicast address register 3 (mar3) 0ch multicast address register 4 (mar4) multicast address register 4 (mar4) 0dh multicast address register 5 (mar5) multicast address register 5 (mar5) 0eh multicast address register 6 (mar6) multicast address register 6 (mar6) 0fh multicast address register 7 (mar7) multicast address register 7 (mar7)
65 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 15. register address assignments page 2 address assignments (ps1 = 1, ps0 = 0) ra3-ra0 read write 00h command register (cr) command register (cr) 01h page start register (pstart) current local dma address 0 (clda0) 02h page start register (pstop) current local dma address 1 (clda1) 03h remote next packet pointer remote next packet pointer 04h transmit page start address (tpsr) reserved 05h local next packet pointer local next packet pointer 06h address counter (upper) (acu) address counter (upper) (acu) 07h address counter (lower) (acl) address counter (lower) (acl) 08h reserved reserved 09h reserved reserved 0ah reserved reserved 0bh reserved reserved 0ch receive configuration register (rcr) reserved 0dh transmit configuration register (tcr) reserved 0eh data configuration register (dcr) reserved 0fh interrupt mask register (imr) reserved note: page 2 registers should only be accessed for diagnostic purposes. they should not be modified during normal operation. page 3 should never be modified.
66 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b register description (continued) 16. dma registers the dma registers are partitioned into three groups: transmit, receive, and remote dma registers, as the diagram shows on the next page. the transmit group contains three registers: tpsr, tbcr0 and tbcr1. registers in this group are used to initialize the local dma channel for transmission of packets. pstart, pstop, curr, bnry, receive byte counter, clda0 and clda1 are located in the receive group. they are used to initialize the local dma channel for packet reception. meanwhile, the page start, page stop, current and boundary registers are also used by the buffer management logic to supervise the receive buffer ring. the remote dma registers are used to initialize the remote dma. six registers are included: rsar0, rsar1, rbcr0, rbcr1, crda0 and crda1. the diagram on the next page shows 8- and 16-bit registers. for slave mode read/write, the 16-bit internal registers are also accessed as 8-bit registers by the host. thus, the 16-bit transmit byte count register is broken into two 8-bit registers, namely, tbcr0 and tbcr1. similarly, remote start address and remote byte count are broken into rsar0, rsar1, and rbcr0, rbcr1. registers tpsr, pstart, pstop, curr and bnry only check or control the upper 8 bits of address informa- tion on the bus. thus, they are shifted to position 15-8, as shown in the diagram on the next page.
67 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b page start transmit byte count local dma channel 15 8 7 0 tpsr tbcr 0, 1 local dma transmit registers local dma receive registers page start page stop current bpimdaru receive byte count current local dma address 15 8 7 0 pstart pstop vurr bnry not readable clda 0, 1 remote dma registers 15 8 7 0 start address byte count current remote dma address remote dma channel bit bit bit rsar 0, 1 rbcr 0, 1 crda 0, 1
68 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b bit assignment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tpsr a15 a14 a13 a12 a11 a10 a9 a8 (a7-a0 initialized to zero) 16. dma registers (continued) transmit dma register (tpsr) this register points to the page where the assembled packet is ready to be transmitted. only the eight higher order addresses are specified since all transmit packets are assembled on 256-byte page boundaries. the bit transmit byte count register 0, 1 (tbcr0, 1) these two registers indicate the length of the packet to be transmitted in bytes. the count must include the number of bytes in the source, destination, length and data fields (crc field is exclusive). the maximum number of trans- mit bytes allowed is 64 kbytes. the enc will not truncate transmissions whenever packet length is longer than 1500 bytes. hence, in order to meet the ieee 802.3 standard, software driver on upper layer must take care of maximum length problem by itself. the bit assignment is shown below: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbcr1 l15 l14 l13 l12 l11 l10 l9 l8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tbcr0 l7 l6 l5 l4 l3 l2 l1 l0 assignment is shown below. the values placed in bits d7- d0 will be used to initialize the higher order address (a15- a8) of the local dma for transmission while the lower order bits (a7-a0) are initialized to zero.
69 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 16. dma registers (continued) local dma receive registers page start/stop registers (pstart, pstop) the page start and stop registers program the starting and stopping page address of the receive buffer ring. since the enc uses fixed 256-byte buffers aligned on page boundaries, only the upper eight bits of the start and stop address are specified. pstart, pstop bit assignment. pstart, bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pstop a15 a14 a13 a12 a11 a10 a9 a8 boundary register (bnry) this register is used to prevent overflow of the receive buffer ring. buffer management compares the contents of this register to the next buffer address when linking buffers together. if the contents of this register match the next buffer address, the local dma operation is aborted and the corresponding bit in isr will be set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bnry a15 a14 a13 a12 a11 a10 a9 a8 current page register (curr) this register is used internally by the buffer management logic as a backup register for reception. curr contains the address of the first buffer to be used for a packet reception, and is used to restore dma pointers if receive errors occur. this register is initialized to the same value as pstart and should not be written to unless the controller is reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 curr a15 a14 a13 a12 a11 a10 a9 a8
70 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 16. dma registers (continued) current local dma register 0, 1 (clda0, 1) the temporary local dma address will be stored in these two registers after each burst transfer is completed. when another burst transfer is ready to start, values within these two registers will be loaded into the address counters (acu and acl) to generate address for local dma channel. these two registers can be accessed to determine the current local dma address. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clda1 a15 a14 a13 a12 a11 a10 a9 a8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clda0 a7 a6 a5 a4 a3 a2 a1 a0 remote dma register remote start address registers (rsar0, 1) remote dma operations are programmed through the remote start address (psar0, 1) and remote byte count (rbcr0, 1) registers. the remote start address is used to point to the start of the block of data to be transferred, while the remote byte count is used to indicate the length of the block (in bytes) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsar1 a15 a14 a13 a12 a11 a10 a9 a8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsar0 a7 a6 a5 a4 a3 a2 a1 a0
71 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 16. dma register (continued) remote byte count registers (rbcr0, 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbcr1 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbcr0 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 note: C rsar1 programs the start address bits a8-a15 C rsar0 programs the start address bits a0-a7 C address incremented by two for word transfers, and by one for byte transfers C rbcr1 programs msb byte count C rbcr0 programs lsb byte count C byte count decremented by two for word transfers, and by one for byte transfers current remote dma address (crda0, 1) the current remote dma registers contain the current address of the remote dma. crda1/0 are similar to clda1/0 except that crda1/0 store the temporary ad- dress of the remote dma. the bit assignment is shown below: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crda1 a15 a14 a13 a12 a11 a10 a9 a8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crda0 a7 a6 a5 a4 a3 a2 a1 a0
72 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b 16. dma register (continued) fifo this is an 8-bit register which allows the cpu to examine the contents of the fifo after loopback. the fifo will contain the last 8 data bytes transmitted in the loopback packet. sequential reads from the fifo will advance a pointer in the fifo automatically and reading of all 8 bytes. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifo db7 db6 db5 db4 db3 db2 db1 db0 note: the fifo should only be read when the enc has been programmed in the loopback mode.
73 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b absolute maximum ratings rating value supply voltage (vcc) 4.75v to +5.5v dc input voltage (vin) -0.5v to vcc +0.5v dc output voltage (vout) -0.5v to vcc +0.5v storage temperature range -65 c to +150 c (tstg) power dissipation (pd) 500 mw lead temp. (tl) 260 c (soldering, 10 sec.) esd rating (rzap=1.5k, 1600v czap=120pf) dc characteristics symbol parameter min. max. unit conditions supply current icc average active (transmitting/receiving) 10 100 ma x1=20mhz clock supply current vin=switching iccidle average idle supply current 10 100 ma x1=20mhz clock vin=vcc or gnd lcclp low power supply current 10 80 ua x1=undriven ttl inputs vil maximum low level input voltage 0.8 v vih minimum high level input voltage 2.0 v iin input current -1.0 1.0 ua vi=vcc of gnd 3sh tri-state high drive i/o voh minimum high level output voltage 2.4 v ioh=-3ma vol maximum low level output voltage 0.5 v iol=24ma vil maximum low level input voltage 0.8 v vih minimum high level input voltage 2.0 v iin input current -1.0 1.0 ua vi=vcc or gnd ioz maximum tri-state output leakage -10.0 10.0 ua vout=vccor gnd current notice: stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended period may affect reliability.
74 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b dc characteristics (continued) symbol parameter min. max. unit conditions mos inputs, outputs and i/o voh minimum high level output voltage vcc-0.1 v ioh=-20ua vol maximum low level output voltage 0.1 v iol=20ua vil maximum low level input voltage 0.8 v vih minimum low level input voltage 2.0 v iin input current -1.0 1.0 ua vi=vcc or gnd iin input current test, dwid pulldown 50 2000 ua vi=vcc register ioz maximum tri-state output leakage -10.0 10.0 ua vout=vcc or gnd current och collector high drive output vol maximum low level output voltage 0.5 v iol=24ma led driver output vol maximum low level output voltage 0.5 v iol=16ma thin driver output voh minimum high level output voltage 2.4 v ioh=-8ma vol maximum low output voltage 0.5 v iol=2ma oscillator pins (x1 and x2) vih x1 input high voltage 2.0 v x1 is connected to an oscillator vil x1 input low voltage 0.8 v x1 is connected to an oscillator iosc x1 input current 1 ma x1 is connected to an oscillator vin=vcc or gnd
75 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b dc characteristics (continued) symbol parameter min. max. unit conditions aui vod differential output voltage (tx ) 550 1250 mv 78 ohm termination and 270 ohm from each to gnd vob differential idle output voltage typical : 40mv mv 78 ohm termination and 270 ohm from each to gnd vu undershoot voltage (tx ) typical : 80mv mv 78 ohm termination and 270 ohm from each to gnd vds diff. squelch threshold (rx , cd ) -175 -300 mv vcm diff. input common mode voltage 0 5.25 v (rx , cd ) tpi rtol txod , txo low level output 15 ohm iol=25ma resistance rtoh txod , txo high level output 15 ohm oh=-25ma resistance vsron1 receive threshold turn-on voltage 300 -585 mv 10base-t mode vsron1 receive threshold turn-off voltage 75 300 mv reduced threshold vsroff receive threshold turn-off voltage 75 300 mv vdiff differential mode input voltage range -3.1 3.1 v vcc=5.0v
76 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac charactristics symbol parameter min. max. unit t1 eecs setup to sk 300 ns t2 eecs hold after sk 300 ns t3 msd2 low time 500 ns t4 msd2 high time 500 ns t5 msd2 clock period 1 m s t6 data in, setup to msd2 high 200 ns t7 data in hold from msd2 high 300 ns serial eeprom timing t1 t2 t5 t4 t7 t3 t6 eecs mdmd2 memd1 mdmd0
77 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac charactristics symbol parameter min. max. unit t1 mema1-15 valid before rscxl asserted (note1) 30 ns t2 mema1-15 valid before msrd/mswr asserted 20 ns t3 msrdl-wrl width 2 bcyc t4 mema1-15 valid to msrdl or mswrl deasserted 40 ns t5 mema1-15 valid after msrdl-wrl 10 ns deasserted t6 rcsxl held after msrdl-wrl deasserted 200 400 ns (note1) t7 rcxl and mema1-15 valid to memd0-15 valid 100 ns t8 read data hold from msrdl deasserted 0 ns t9 write data set-up to mswrl deasserted 60 ns t10 write data held from mswrl deasserted 10 ns t11 time between transfers 4 bcyc t12 minimum bus clock high time (bch) 10 ns t13 minimum bus clock low time (bcl) 20 ns t14 minimum bus clock cycle time (bcyc) 50 ns note 1 : in 8-bit mode rcsxl refers to rcs1l only. in 16-bit mode rcsxl refers to both rcs1l and rcs2l. memory support bus accesses (for i/o port or fifo transfers) bsck mema1-15 rcsxl msrdl or mswrl t12 t13 t14 t1 t11 t4 t5 t6 t2 t3 t7 t8 t9 t10 t1 t2 t3 t4 t1 memd0-15 (read) memd0-15 (write)
78 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b isa slave accesses bale aen la17-23 m16l, io16l chrdy t6c t1 t15 t19 t2 t22 t21 t6a, b t13 t16 t18 t7 t14 t8 t5b t5a t23 t5c t4 t3 t17 t10 t9 t20 t11 data valid t27 t35 t12 t30 t28 t36 t31 t32 t37 address valid t34 t29 t25 t24 t26 t33 t38 sbhe sa0-9 mrdl, mwrl, smrdl, smwrl, iordl, iowrl sd0-15 (read) sd0-15 (write) rcsxl or bpcsl msrdl, mswrl mema1-15 memd0-15 (read) memd0-15 (write)
79 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac charactristics symbol parameter 8 bit 16 bit unit min. max. min. max. t1 bale width 20 20 ns t2 aen valid before command 40 40 ns strobe active t3 sbhel & sa0-9 valid before command 20 20 ns asserted t4 iordl, mrdl asserted to sd0-15 driven 0 0 ns (note 3) t5a sbhel & sa0-9 valid before io16l valid 45 ns (notes 1 & 9) t5b la17-23 valid to m16l valid (note 1) 30 ns t5c sbhel & sa0-9 valid and iordl or iowrl 20 ns active before io16l valid (notes 1 & 10) t6a iordl, iowrl asserted to chrdy negated 35 35 ns (notes 2 & 5) t6b mrdl, mwrl asserted to chrdy negated 35 35 ns (note 2) t6c bale asserted & sa0-9 valid to chrdy 15 15 ns negated (notes 2 & 4) t7 iordl deasserted before 15 15 ns sbhel & sa0-9 invali t8 la17-23 invalid to m16l invalid (note 1) 0 ns t9 iordl, mrdl deasstered to sd0-15 0 0 ns (note 3)read data invalid t10 iordl, mrdl deasserted to sd0-15 30 30 ns floating (note 3) t11 d0-15 write data valid to iowrl 60 20 ns deasstered (note 3) t12 iowrl, mwrl negated to sd0-15 write data 15 15 ns invalid (note 3) t13a iordl, iowrl active width (note 3) 300 140 ns t14a iordl, iowrl inactive width 85 85 ns t14b mrdl, mwrl inactive width smrdl, smwrl
80 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac charactristics (continued) symbol parameter 8 bit 16 bit unit min. max. min. max. t15 bale asserted before mrdl, mwrl 25 ns asserted t16 mrdl, mwrl deasserted before next bale 20 ns asserted t17 chrdy asserted to sd0-15 i/o read data 60 60 ns valid (notes 2, 3, & 6) t18 iordl, iowrl negated before aen invalid 25 50 ns t19 aen valid before bale deassereted 50 25 ns t20 iordl asserted to sd0-15 read data valid (notes 3 & 7) 150 150 ns t21 la17-23 valid before bale negated t22 bale negated before la17-23 invalid t23 la17-23 valid before mrdl, mwrl asserted t24 read data valid on msd0-15 to valid on sd0-15 40 40 ns t25 msrdl deasserted to msd0-15 read 0 0 ns data invalid (note 3) t26 write data valid on sd0-15 to valid on 30 30 ns memd0-15 t27 sa0-19 valid to /rcs xl or /bpcsl asserted 40 40 ns (note 11) t28 mrdl, mwrl asserted to msrdl, mswrl 30 30 ns asserted t29 sa0-19 valid to mema1-15 valid 30 30 ns t30 sa0-19 invalid to rcsxl or bpcsl negated 30 20 ns (note 11) t31 mrdl, mwrl deasserted to msrdl, 0 30 0 45 ns mswrl deasserted t32 mswrl deasserted to mema1-15 10 10 ns invalid
81 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac charactristics (continued) symbol parameter 8 bit 16 bit unit min. max. min. max. t33 mswr1deasserted to msmd0-15 20 20 ns invalid (note 3) t34 mema1-15 valid before /mswrl 20 20 ns asserted t35 rcsxl or /bpcsl asserted to chrdy 15 15 ns asserted (note 11) t36 msrdl, mswrl asserted to chrdy 0 0 ns asserted t37 mema1-15 valid to chrdy asserted 15 15 ns t38a driving data from sd0-15 on to 60 60 ns memd0-15 to chrdy asserted for ram access t38b driving data from sd0-15 to chrdy 260 260 ns asserted for boot prom access note 1: m16l, io16 are only asserted for 16-bit transfers. note 2: chrdy is only deasserted if the nic core cannot service the access immediately. it is held deasserted until the nic core is re ady, causing the system to insert wait states. note 3: on 8-bit trnasfers only 8 bits of mehd0-15 and d0-7 are driven. note 4: this is the earty chrdy timing required by some machines, where chrdy is referenced to bale. in this mode of operation, under certain circumstances, chrdy will be asserted for cycles which are not for this device i.e., memory cycles or i/o cycles where sa0-9 match our address before reaching their valid state. in such a case the time to assert chrdy, from mrdl, mwrl or sa0-9 invalid , will be the same as the deassertion time specified. note 5: this is the standard chrdy timing where chrdy is asserted after iordl or iowrl. note 6 : read data valid is referenced to chrdy when wait states have been inserted. note 7: if no wait states are inserted read data valid can be measured from iordl. note 8: this is a minimum timing with no additional wait states. note 9: this is the standard i/o 16 timing where /io16 is asserted after a valid address decode and iordl or iowrl going active. note 10: this is the late io16l timing, required by some machines. where io16l is asserted after a valid address decode and iordl or iowrl going active. note 11: bpcs is asserted for a boot prom access. rcsl for a ram access. rcsxl refers to rcs1l and rcs2l depending on the mode of operation either or both can be asserted. see the functional bus timing section for further explanation. note 12: specifications which measure delays from an active state to a high impedance state are not guaranteed by production test, but a re characterized and correlated to determine true driver turn-off time by simulating inherent r-c delay times. in test measuremen ts.
82 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac characteristics (continued) symbol parameter min. max. unit ttoh transmit output high before (half step) 200 ns ttol transmit output idle time (half step) 8000 ns aui transmit timing (end-of-packet) txp txm txp txm 10 1 10 0 ttoi ttoh symbol parameter min. max. unit teop1 receive end-of-packet hold time 250 ns after logic "1" (note 1) teop 0 receive end-of-packet hold time 250 ns after logic "0" (note 1) note: 1. this parameter is guaranteed by design and is not tested. aui/api receive end-of-packet timing rxp or rxip rxm or rxim rxp or rxip rxm or rxim teop1 teop0 00 11
83 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac characteristics (continued) symbol parameter min. max. unit tdel pre-emphasis output delay 46 54 ns (txop,txom to txodp,txodm) (note 1) toff transmit hold time at end-of-packet 250 ns (txop,txom) (note 1) toffd transmit hold time at end-of-packet 200 ns (txodp,txodm) (note 1) note: 1. this parameter is guaranteed by design and is not tested. tpi transmit and end-of-packet timing txop txodp txom txodm txop txodp txom 1 0 1 tdel toff toffd tdel 10 1 toffd toff txodm
84 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b ac characteristics (continued) symbol parameter min. max. unit tip time between link output pulses 8 24 ms tipw link integrity output pulse width 80 130 ns link pulse timing txop txodp txom txodm tipw tip ordering information part no. package MX98905BFC 160 pin pqfp
85 p/n: pm0365 rev. 1.3, nov 20 ,1995 mx98905b package information 160-pin pqfp f n m k l j p o ecd 40 1 80 81 120 121 160 41 i h g b a item millimeters inches a 31.20 .30 1.228 .012 b 28.00 .10 1.102 .004 c 28.00 .10 1.102 .004 d 31.20 .30 1.228 .012 e 25.35 .999 f 1.33 [ref] .052 [ref] g 1.33 [ref] .052 [ref] h .30 [typ.] .12 [typ.] i .65 [typ.] .026 [typ.] j 1.60 [ref] .063 [ref] k .80 .20 .031 .008 l .15 [typ.] .006 [typ.] m .10 max. .004 max. n 3.35 max. .132 max. o .10 min. .004 min. note: each lead centerline is located within .25mm[.01 inch] of its true position [tp] at a maximum material condition.
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 86 mx98905b

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